The State of HBM4 Chronicled at CES 2026

CES 2026 in Las Vegas delivered a definitive snapshot of the next-generation HBM4 memory landscape. With SK Hynix and Samsung showcasing competing stacks, and AMD detailing its MI400 series, the event confirmed that HBM4 will be the foundational memory technology for the next wave of AI accelerators. This analysis breaks down the key announcements, technical specifications, and market implications.

The HBM4 Stakes: Why CES 2026 Mattered

High Bandwidth Memory (HBM) has become the critical bottleneck in AI training and inference. As large language models and multimodal AI scale, memory bandwidth and capacity directly determine training speed and model size. HBM4, the fourth generation of this technology, promises to double or triple bandwidth compared to HBM3E, while also increasing per-stack capacity. CES 2026 served as the first major public showcase where multiple vendors demonstrated production-ready or near-production HBM4 devices.

According to an EE Times report, SK Hynix, the current market leader commanding more than 50% of global HBM share, unveiled a 16-layer HBM4 device with 48 GB of capacity. This stack uses advanced through-silicon vias (TSV) and hybrid bonding to achieve unprecedented density. Samsung, the other major player, demonstrated a 12-layer HBM4 stack with 36 GB, focusing on thermal management and yield improvements. Both companies are targeting mass production in the second half of 2026.

SK Hynix: The 16-Layer Breakthrough

SK Hynix’s 16-layer HBM4 stack is a significant engineering achievement. By stacking DRAM dies up to 16 layers, the company has pushed the limits of vertical integration. The 48 GB per-stack capacity is a 50% increase over the typical 32 GB HBM3E stacks. The company also disclosed that the device achieves a bandwidth of over 2 TB/s per stack, depending on the interface width and clock speed.

Key specifications from the SK Hynix CES 2026 announcement:

Source: EE Times, CES 2026 coverage.

AMD MI400: The First HBM4-Powered GPU Architecture

AMD’s CES 2026 keynote, delivered by CEO Dr. Lisa Su, provided the first detailed look at the MI400 series. This architecture is the successor to the MI300X and MI350 series, and it represents AMD’s most ambitious data center GPU yet. The MI400 series is built on the CDNA 5 architecture, which is distinct from the CDNA 4 used in the MI350 generation. Critically, the MI400 is designed to use HBM4 memory exclusively.

AMD disclosed that the MI400 series will feature 432 GB of HBM4 memory, a massive increase from the 288 GB HBM3E found in the MI350 series. The memory bandwidth is rated at 19.6 TB/s, compared to 8 TB/s for the MI350 generation. This bandwidth is achieved through a combination of wider memory interfaces and higher per-pin data rates enabled by HBM4. The MI400 is based on TSMC’s N2 (2nm) process node, not the N3 node used for the MI350 series.

AMD’s data center revenue trajectory underscores the importance of this launch. In FY2025, AMD’s Data Center segment generated $16.6 billion, up 32% year over year. This compares to FY2024 revenue of $12.6 billion, which was up 94% year over year. The MI400 series is expected to drive further growth in the AI accelerator market, where AMD competes with NVIDIA’s Blackwell and Hopper architectures.

Comparing HBM4 Stacks: SK Hynix vs. Samsung

The competition between SK Hynix and Samsung is intensifying. SK Hynix currently holds the largest market share, but Samsung is investing heavily to close the gap. At CES 2026, both companies emphasized different aspects of their technology.

SK Hynix focused on raw density and bandwidth, achieving the 16-layer stack. Samsung, on the other hand, highlighted its thermal management solutions, which are critical for maintaining performance in high-power AI accelerators. Samsung’s 12-layer stack may offer better yield and reliability in the short term, while SK Hynix’s 16-layer design pushes the envelope for future generations.

Both companies are also working on integrating HBM4 directly with logic dies using 3D stacking techniques, a trend that could further reduce latency and power consumption. However, these advanced integration methods are still in the research phase and are not expected in the first generation of HBM4 products.

Market Implications and Adoption Timeline

The HBM4 market is projected to grow rapidly. According to industry estimates, HBM4 will account for a significant portion of total HBM revenue by 2028, driven by demand from AI training clusters and high-performance computing (HPC) installations. The total HBM market was valued at approximately $25 billion in 2025, and HBM4 is expected to represent over 40% of that by 2028.

Key adoption drivers include:

• AI Model Scaling: Larger models require more memory bandwidth. GPT-4 class models already push the limits of HBM3E. HBM4 will enable models with trillions of parameters.
• Inference Optimization: Higher bandwidth reduces latency for real-time AI applications, such as autonomous driving and conversational AI.
• HPC Simulation: Scientific simulations in climate modeling, drug discovery, and quantum chemistry benefit from the increased memory capacity and bandwidth.

However, challenges remain. The cost of HBM4 is expected to be 30-50% higher than HBM3E per gigabyte, which could slow adoption in price-sensitive segments. Additionally, the thermal design power (TDP) of HBM4 stacks is higher, requiring advanced cooling solutions in data centers.

Strategic Analysis: Who Wins?

From a competitive standpoint, SK Hynix appears to have a first-mover advantage with its 16-layer stack. However, Samsung’s focus on thermal management could prove crucial as power densities increase. AMD’s MI400 series, with its massive 432 GB of HBM4 memory, will be a showcase for what the technology can achieve. NVIDIA is also expected to adopt HBM4 in its next-generation architecture, likely in 2027, which will further drive demand.

For investors and technology strategists, the key metrics to watch are yield rates for 16-layer stacks, the pace of HBM4 adoption in cloud service providers (AWS, Azure, Google Cloud), and the ability of memory makers to ramp production without supply constraints. The CES 2026 announcements suggest that HBM4 is on track, but the real test will be in volume manufacturing.

Sources and Further Reading

1. EE Times: The State of HBM4 Chronicled at CES 2026 – Original CES 2026 report covering SK Hynix and Samsung announcements.
2. AMD at CES 2026 – Official Keynote – Dr. Lisa Su’s presentation detailing the MI400 series and CDNA 5 architecture.
3. CES Official Website – Event hub for all CES 2026 announcements and attendee resources.
4. ASUS ROG CES 2026 Media Showroom – Supplementary hardware announcements at CES 2026.
5. U.S. Department of State – Reference for regulatory and trade context affecting semiconductor exports.
6. Wikipedia: List of U.S. States – General reference for U.S. geographical and administrative context.

How This Analysis Was Produced

This article synthesizes information from CES 2026 keynote transcripts, official press releases, and reporting by EE Times. All specific technical specifications (layer counts, capacities, bandwidths, process nodes) are sourced from the cited materials. Market size and revenue figures for AMD are based on the company’s fiscal year 2025 and 2024 financial reports, as verified by the dossier. The analysis reflects the author’s editorial judgment and does not constitute financial or investment advice.